ASIC Architect

Quantum Dice Ltd.; Oxford, Greater London; Hybrid; GBP 70,000 - 90,000; Full time

Job summary

A pioneering technology company in England is seeking an experienced candidate to lead the ASIC strategy of their cutting-edge probabilistic computing platform. This role includes overseeing ASIC design and integration with hardware, managing relationships with foundries, and ensuring optimal performance. Candidates with a proven track record in managing ASIC projects and strong communication skills are encouraged to apply. This is a unique opportunity to work in an innovative field shaping the future of computing.

Qualifications

• Proven track record managing ASIC projects from concept to production.
• Experience in heterogeneous computing systems and hardware-software co-design.
• Strong understanding of interface protocols.

Responsibilities

• Define and own high-level system architecture.
• Oversee ASIC design lifecycle from specification to implementation.
• Manage relationships with semiconductor foundries.

Skills

Strong understanding of system architecture

Knowledge of ASIC design flow

Ability to assess trade-offs between ASIC and FPGA

Excellent communication skills

Job description

About the Role

We are seeking an experienced candidate to lead the miniaturisation of our cutting‑edge probabilistic computing platform. This role is pivotal in defining and executing the ASIC strategy, ensuring optimal integration with other processing units such as FPGAs and GPUs. You will work closely with hardware engineers, algorithm designers, and fabrication partners to deliver a high‑performance, cost‑effective solution.

We welcome all qualified international candidates to apply for this role. We have offices in Oxford and London, and are open to other international locations.

Key Responsibilities

• ASIC strategy & architecture
  • Assess system components to determine which should be implemented as ASIC versus FPGA or GPU.
  • Define ASIC architecture in alignment with overall system requirements, including interfaces and memory hierarchy.
  • Evaluate trade‑offs between different processing units (ASIC, FPGA, GPU, SoC) for performance, power, and scalability.
• Architectural planning
  • Define and own high‑level system architecture, refining requirements into functional, logical, and physical interfaces and constraints.
  • Lead partitioning decisions (analogue vs. digital domain, as well as core compute, memory and IO subsystems, chiplet selection, placement and interconnect strategy).
  • Oversee internal and third‑party IP for design blocks, chiplets, PDKs, chip‑to‑chip and die‑to‑die interfaces.
  • Drive top‑level floor planning.
  • Direct functional simulations and co‑simulation across multiple domains.
• Design & development
  • Oversee ASIC design lifecycle: specification, RTL design, verification, and physical implementation.
  • Ensure compatibility with system‑level interfaces and integration requirements.
• Fabrication & packaging
  • Manage relationships with semiconductor foundries and packaging vendors.
  • Coordinate fabrication, packaging, and testing processes to meet performance and reliability targets.
• Integration & validation
  • Lead integration of ASIC components into the broader computing platform.
  • Collaborate with software and hardware teams to validate functionality and optimise performance.
• Project management
  • Define milestones, budgets, and resource allocation for the ASIC workstream.
  • Report progress and risks to senior leadership.

Required qualifications

• Technical expertise
  • Strong understanding of system architecture, memory requirements, and interface protocols.
  • Knowledge of ASIC design flow, including synthesis, place‑and‑route, and verification.
  • Familiarity with FPGA and GPU architectures and their respective advantages.
• Experience
  • Proven track record managing ASIC projects from concept to production, including fabrication and packaging.
  • Experience in heterogeneous computing systems and hardware‑software co‑design.
• Skills
  • Ability to assess trade‑offs between ASIC, FPGA, and GPU implementations.
  • Excellent communication and leadership skills for cross‑functional collaboration.

Preferred qualifications

• Experience with probabilistic or unconventional computing architectures.
• Familiarity with advanced packaging technologies (e.g., chiplets, 2.5D/3D integration).
• Knowledge of low‑power design techniques and high‑speed interfaces.

Why Join Us?

You’ll be at the forefront of next‑generation computing, shaping a platform that redefines performance and efficiency. This is an opportunity to lead innovation in a rapidly evolving field.