Hybrid Verification Engineer – System IP (RTL/UVM)

Arm; Cambridge; Hybrid; GBP 50,000 - 70,000; Full time

Job summary

A leading technology company in Cambridge seeks an experienced verification engineer to join their System IP team. The role involves owning the verification process, developing strategies, and improving existing testbenches. Candidates should have substantial experience in ASIC products, proficiency in System Verilog / UVM, and strong communication skills. The job allows for hybrid working, offering flexibility and team collaboration.

Benefits

Hybrid working model

Accommodations for applicants

Equal opportunity employer

Qualifications

• Experience in RTL verification of ASIC products.
• Proficiency in a hardware verification language, preferably System Verilog / UVM.
• Understanding of computer architecture fundamentals.

Responsibilities

• Own the verification of a unit through all phases of design and verification.
• Develop comprehensive verification strategies with the RTL design team.
• Create and implement verification IP and testbenches.

Skills

RTL verification of complex ASIC products

System Verilog / UVM

Development of coverage-driven constrained random test environments

Strong communication skills

Computer architecture fundamentals

Tools

SystemVerilog

Verilog

Python or Perl

Job description

A leading technology company in Cambridge seeks an experienced verification engineer to join their System IP team. The role involves owning the verification process, developing strategies, and improving existing testbenches. Candidates should have substantial experience in ASIC products, proficiency in System Verilog / UVM, and strong communication skills. The job allows for hybrid working, offering flexibility and team collaboration.