VHDL Design Engineer Electrical Engineering · Guildford

Surrey Satellite Technology Ltd.; Guildford; On-site; GBP 45,000 - 60,000; Full time

Job summary

A leading satellite technology company in Guildford is seeking a Design Engineer to design, implement, and verify FPGA designs using VHDL. The role involves working closely in a project team, conducting simulations, and ensuring requirements are met. Candidates should have several years of experience in FPGA design, excellent communication, and commitment to tight schedules.

Qualifications

• Several years experience of FPGA design.
• Experience of system level debug and test.
• Commitment to deliver to challenging schedules.

Responsibilities

• Design, develop, and simulate FPGA designs in VHDL.
• Translate mission requirements down to FPGA implementation.
• Perform simulation, synthesis and timing analysis.

Skills

FPGA design

VHDL

Excellent communication skills

System level debugging

Tools

Lab Test Equipment

Job description

Reports ToOBDH Team Leader

Key PurposeOf Job

The design engineer will design, implement, and verify FPGA designs using VHDL.

Key Tasks

• Design, develop, and simulate FPGA designs in VHDL

• Take mission requirements and translate down to FPGA implementation

• Perform simulation, synthesis and timing analysis to verify functionality and performance

• Create testbenches for functional verification

• Generation of appropriate design documentation

• Work closely in a core project team.

• Responsible for the delivery of all aspects of the defined/delegated package of work which includes, Technical Solution, Budget and Schedule.

PERSON SPECIFICATION (essential requirements)

Experience

• Several years experience of FPGA design.

• Experience of system level debug and test

Knowledge & Skills

• Knowledge of FPGA design in VHDL

• Knowledge of Lab Test Equipment

• Excellent communication skills

• Commitment to deliver to challenging schedules

• Good inter-personal skills

• Organised approach

• Good planning skills

Additional responsibilities

• Involvement in SSTL peer reviews