Staff Engineer, Design Verification — SoC Validation Lead

Analog Devices, Inc.; City of Edinburgh; On-site; GBP 50,000 - GBP 70,000; Full time

Job summary

A global semiconductor leader is seeking a Staff Engineer for Design Verification in Scotland. This role involves verifying complex designs, developing testbench architectures, and collaborating with a diverse technical team. The ideal candidate will have a degree in Electronic Engineering, significant experience in ASIC design verification, and strong skills in verification methodologies. The position offers a chance to work with cutting-edge technologies and mentor junior engineers.

Qualifications

• 5-10 years in ASIC design verification.
• Strong knowledge of verification-plan generation and constrained random techniques.
• Proficient in developing unit and SoC level test benches using UVM.

Responsibilities

• Contribute to verification of complex designs and sub-systems.
• Develop testbench architectures and verification plans.
• Mentor junior verification engineers.

Skills

Verification of complex designs

Testbench architecture development

Debugging skills

Proficiency in scripting languages

Excellent analytical skills

Education

Bachelor's or Master’s degree in Electronic Engineering

Tools

System Verilog

UVM

Python

Perl

Job description

A global semiconductor leader is seeking a Staff Engineer for Design Verification in Scotland. This role involves verifying complex designs, developing testbench architectures, and collaborating with a diverse technical team. The ideal candidate will have a degree in Electronic Engineering, significant experience in ASIC design verification, and strong skills in verification methodologies. The position offers a chance to work with cutting-edge technologies and mentor junior engineers.