Design Verification Manager

microTECH Global Limited; Cambridge; On-site; GBP 100,000 - 125,000; Full time

Job summary

A semiconductor design firm in Cambridge is seeking a Design Verification Manager to lead a multi-site team on complex IC projects. This role requires strong expertise in silicon design verification and UVM, along with leadership experience. The position offers a competitive salary, benefits, and opportunities for professional development.

Benefits

25 days annual leave + 8 bank holidays

12.5% employer pension contribution

4-week paid sabbatical after 4 years

Private Medical Insurance

Opportunities to attend industry conferences

Qualifications

• Strong expertise in silicon design verification, UVM, and formal verification required.
• Extensive experience with SystemVerilog needed.
• Proficiency in Python for scripting and automation is essential.

Responsibilities

• Lead and mentor a multi-site design verification team.
• Define and execute verification strategies for digital blocks.
• Own and improve verification methodologies and flows.

Skills

Silicon design verification

UVM

Formal verification

SystemVerilog

Python

Constrained-random testing

Leadership

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering

Job description

We’re looking for a Design Verification Manager to lead a high-performing, multi-site team working on complex, production-ready IC projects in Cambridge, UK.

Job Title: Design Verification Manager
Location: Cambridge, UK
Employment Type: Permanent

Salary: Competitive and negotiable

About the Company

Our client is a non-profit, open-source hardware organization dedicated to making production-ready semiconductor IP and engineering systems freely available, transforming the semiconductor industry.

Their flagship projects have reached production silicon in collaboration with companies like Google and Rivos. Teams are based in Cambridge, UK, and Zurich, Switzerland.

Role Overview

The Design Verification Manager leads the verification of complex ICs, manages a multi-site team, and drives methodology adoption across projects. The role is primarily managerial, with technical contributions, particularly in collaboration with customers.

Key Responsibilities

• Lead, mentor, and develop a multi-site DV team (hiring, performance reviews, resource allocation)
• Define and execute verification strategies for digital blocks and full-chip verification
• Own and improve verification methodologies (e.g., UVM) and flows
• Provide technical guidance to ensure alignment with architectural goals and timelines
• Collaborate with engineers, architects, and customers to ensure verification quality
• Track verification risks and progress toward tape‑out
• Maintain a high-level overview of project status, technical challenges, and team interactions

Required Skills & Experience

• Strong expertise in silicon design verification, UVM, and formal verification
• Extensive experience with SystemVerilog
• Proficiency in Python for scripting and automation
• Experience with constrained‑random testing and advanced verification techniques
• Proven leadership experience managing remote/multi‑site teams
• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or equivalent

Benefits

• 25 days annual leave + 8 bank holidays
• 12.5% employer pension contribution (subject to 6% employee salary sacrifice)
• 4-week paid sabbatical after 4 years
• Private Medical Insurance, Group Income Protection, Critical Illness, Life Insurance
• Opportunities to attend industry conferences and training

If interested, please get in touch and send your CV over to [e-mail]