Senior SoC Design Engineer - RTL, Power & Timing

Arm; Cambridge; Hybrid; GBP 50,000 - 80,000; Full time

Job summary

A leading technology firm is seeking a creative and enthusiastic SoC Design Engineer. The role focuses on developing subsystems using Arm's latest IP products, requiring expertise in RTL design, micro-architecture specifications, and complex ASIC products. Ideal candidates will have experience with power management and computer architecture fundamentals. The position offers a competitive reward package, including an annual bonus and wellness support. Join us in a hybrid working environment tailored to performance and well-being.

Benefits

Annual bonus

Healthcare and wellness support

Supplementary pension

25 days annual leave

Qualifications

• 5+ years of experience in RTL design for ASICs and SoCs using Verilog and/or SystemVerilog.
• Knowledge of power domain and clock domain crossing implementation.
• Experience with programming languages such as Tcl, Perl, or Python.

Responsibilities

• Write micro-architecture specifications.
• Develop RTL and run design checks.
• Work with verification team to review test plans.

Skills

RTL design for complex ASIC products

Static design checks

Synthesis and timing analysis

Power management techniques

Computer architecture fundamentals

Shell programming/scripting

Job description

A leading technology firm is seeking a creative and enthusiastic SoC Design Engineer. The role focuses on developing subsystems using Arm's latest IP products, requiring expertise in RTL design, micro-architecture specifications, and complex ASIC products. Ideal candidates will have experience with power management and computer architecture fundamentals. The position offers a competitive reward package, including an annual bonus and wellness support. Join us in a hybrid working environment tailored to performance and well-being.