IC Package Designer

microTECH Global Limited; Cambridge; On-site; GBP 45,000 - 70,000; Full time

Job summary

A semiconductor design firm in Cambridge is seeking an IC Package Designer to develop innovative and high-performance packaging solutions. The ideal candidate will have 3–8+ years of experience in IC package design and proficiency in Cadence Allegro Package Designer. The role involves designing substrates and ensuring signal integrity for advanced technologies. This position offers a long-term contract with competitive benefits.

Qualifications

• 3–8+ years of experience in IC package design and development.
• Hands-on experience in wire bond, flip-chip, and advanced packaging technologies.

Responsibilities

• Create netlists and BGAs according to project requirements.
• Conduct feasibility studies to recommend optimal pad layouts.
• Define substrate stack-ups and routing strategies.

Skills

IC package design

RF design

Signal integrity

Power integrity

Cadence Allegro Package Designer

Education

Bachelor’s degree in Electronics or Electrical Engineering

Tools

Cadence Allegro Package Designer

Job description

Job Title: IC Package Designer
Location: Cambridge, UK
Contract Type: Long-term Contract

We are seeking an experienced IC Packaging Designer to join our clients team in Cambridge. This role offers the opportunity to develop creative, cost-effective, and high-performance IC packaging designs for cutting-edge semiconductor applications.

Key Responsibilities:

• Create netlists and BGAs according to project requirements.
• Conduct feasibility studies to recommend optimal pad layouts, interconnect types, and substrate parameters for specific IC devices or applications.
• Define substrate stack-ups, routing strategies, and via structures.
• Design substrates for RF, digital, high-speed, and mixed-signal dies.
• Ensure signal integrity (SI) and power integrity (PI) requirements for high-speed interfaces (DDR, SERDES, etc.).
• Work with UCIE-Advanced, standard technologies, and HBM technologies.
• Set design rule checks (DRC) to ensure layouts meet manufacturing, assembly, and design guidelines.
• Optimize die breakout for signals and create patterns for high-power applications.
• Apply expertise in HDI substrate technologies, layout rules, and materials for optimal electrical, thermal, mechanical, and manufacturability performance.
• Demonstrate knowledge of different package types and OSAT design rules.
• Design wire bond and flip-chip substrates, including advanced packaging technologies such as 2.5D, 3D, RDL, and embedded passives.
• Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and understanding of substrate impact on CoWoS performance.

Qualifications & Experience:

• Bachelor’s degree in Electronics or Electrical Engineering.
• 3–8+ years of experience in IC package design and development.
• Proficiency in Cadence Allegro Package Designer.
• Hands-on experience in wire bond, flip-chip, and advanced packaging technologies.

Please get in touch with Christina McGuire to hear more!