FPGA/ASIC Design Verification Engineer — FinTech

G-Research; City of London; On-site; GBP 100,000 - 125,000; Full time

Job summary

A leading quantitative finance firm in London seeks a Design Verification Engineer to join its Software Engineering team. You will oversee the application of formal verification tools, develop co-simulation environments and maintain complex verification setups. Ideal candidates should have extensive FPGA/ASIC design experience, knowledge of standard interfaces, and a background in fintech is beneficial. The role offers highly competitive compensation, annual leave, and workplace benefits.

Benefits

Highly competitive compensation

Annual discretionary bonus

Lunch provided

35 days’ annual leave

9% company pension contributions

Comprehensive healthcare and life assurance

Cycle-to-work scheme

Monthly company events

Qualifications

• Extensive experience of large FPGA and ASIC design.
• Comfortable writing test plans, creating test benches and analysing code coverage.
• Excellent knowledge of industry standard interfaces and build tools.

Responsibilities

• Develop System Verilog based VMM/UVM test bench environments.
• Develop assertion based formal verification.
• Develop co-simulation environments to verify between C/C++ models and RTL modules.
• Write test plans, create test bench specifications and analyse code coverage.
• Implement constrained-random sequences, agents and environments using UVM methodology.
• Develop and maintain complex verification environments using different methodologies.

Skills

Knowledge of industry-standard interfaces

Experience with industry-standard build tools

Knowledge of QuestaSim environment

Extensive experience with large FPGA/ASIC designs

Background in fintech

Job description

A leading quantitative finance firm in London seeks a Design Verification Engineer to join its Software Engineering team. You will oversee the application of formal verification tools, develop co-simulation environments and maintain complex verification setups. Ideal candidates should have extensive FPGA/ASIC design experience, knowledge of standard interfaces, and a background in fintech is beneficial. The role offers highly competitive compensation, annual leave, and workplace benefits.