ASIC Engineer, Design

Meta; Garden City (ID); On-site; USD 142,000 - 203,000; Full time

Job summary

A leading tech company is hiring ASIC Design Engineers to work in innovative fields like machine learning and video processing. Candidates should have significant experience in micro-architecture development and RTL design, with a focus on collaboration across teams. This role offers a competitive salary range of $142,000 to $203,000 annually, plus bonuses and benefits.

Benefits

Bonus

Equity

Comprehensive benefits

Qualifications

• 6+ years of experience in micro-architecture and RTL development for complex control and data path IPs.
• Experience in SoC Micro-architecture, Design and Integration.
• Experience in data path development.

Responsibilities

• Build cutting-edge ASICs in machine learning, video transcoding, and network acceleration.
• Conduct architecture exploration.
• Collaborate with teams for design closure on timing and power.

Skills

ASIC Engineer

Micro-architecture development

RTL development using Verilog

Collaboration with verification teams

Education

Bachelor's degree in Computer Science or related field

Master's or PhD degree in Electrical Engineering or related areas

Tools

Verilog

System Verilog

Job description

Summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required Skills

1. ASIC Engineer, Design Responsibilities:

2. Architecture exploration

3. Micro-architecture development

4. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug

5. Collaboration with implementation team to close the design on timing and power

Minimum Qualifications

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. 6+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration

3. RTL development using Verilog, System Verilog and HLS

Preferred Qualifications

1. Experience in CPU, NOC, Memory and Peripheral Subsystems

2. Experience with Synthesis, Timing Closure and Formal Verification Methodology

3. Master’s or PhD degree in Electrical Engineering, Computer Science or related areas

4. Experience in data path development

Public Compensation

$142,000/year to $203,000/year + bonus + equity + benefits

Industry

Internet

Equal Opportunity

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].