Senior ASIC Verification Engineer

Swediumglobal; Stockholm; On-site; SEK 450 000 - 750 000; Full time

Job summary

An innovative company is seeking a skilled verification engineer to lead advancements in telecommunications. As part of a dynamic ASIC IP team, you will shape the future of connectivity through the development of high-quality IPs for 5G and 6G technologies. This role emphasizes creativity, collaboration, and a commitment to continuous improvement, making it an exciting opportunity for those passionate about making a real-world impact. Join a culture that thrives on innovation and be at the forefront of technological advancements in the industry.

Qualifications

• 15 years of experience in ASIC or FPGA verification at various levels.
• Hands-on experience with UVM test environments and coverage closure.

Responsibilities

• Develop comprehensive verification planning and specifications.
• Architect and enhance state-of-the-art verification environments.
• Drive testing strategies to uncover hidden bugs.

Skills

ASIC verification

FPGA verification

SystemVerilog UVM

UVM test environments

Creative problem-solving

Communication skills

Continuous improvement mindset

Education

Master’s degree in Electrical Engineering

Master’s degree in Computer Engineering

Job description

Swedium Global is a growing System Engineering and Solution Company, offering services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy, and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global has a presence in Sweden, Finland, Poland, Czech Republic, and India.

Location: Sweden

We are looking for an experienced verification engineer to lead innovation in the ever-evolving world of telecommunications. As a member of our ASIC IP team, the candidate will be instrumental in shaping the 5G and 6G waves. Experience and insight will play a pivotal role in ensuring the delivery of high-quality IPs that shape the future of global connectivity. Expertise will be critical in turning game-changing ideas into real-world solutions that will shape the future of connectivity while being part of a culture that thrives on creativity, collaboration, and making a real-world impact.

What the candidate will do:

1. Develop a comprehensive verification planning, including specifications.
2. Architect and enhance state-of-the-art verification environments.
3. Implement and maintain UVCs, ensuring every corner of the design is verified.
4. Drive both random and directed testing strategies to uncover hidden bugs.
5. Leverage advanced coverage techniques to ensure top-tier verification completeness.
6. Champion continuous improvement in product quality, efficiency, and workflows.

Skills to bring:

1. Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM. Possibly 15 years of experience in Verification.
2. Hands-on experience designing UVM test environments and driving coverage closure.
3. An insatiable curiosity, ready to learn something new daily and apply it to make a real difference.
4. Creative problem-solving skills—you see challenges as opportunities for innovation.
5. A collaborative spirit and the ability to thrive independently, with exceptional communication skills.
6. A results-oriented mindset with a passion for continuous improvement, always seeking more innovative, faster solutions.
7. A Master’s degree in Electrical Engineering, Computer Engineering, or a related field.