Cellular IP Design Engineer (m/f/d)

Apple Inc.; München; Vor Ort; EUR 60.000 - 100.000; Vollzeit

Zusammenfassung

An established industry player is seeking a skilled IP Design Engineer to join their Cellular SoC IP team in Munich. In this dynamic role, you will develop and integrate customized hardware IPs for digital signal processing, working closely with diverse teams to ensure optimal performance and power efficiency. Your responsibilities will span the entire project lifecycle, from concept to in-field operation, allowing you to make a significant impact on cutting-edge technology. If you are passionate about innovative design and thrive in a collaborative environment, this opportunity is perfect for you.

Qualifikationen

• Experience with low-power hardware design and digital signal processing.
• Proficient in Verilog/System Verilog and debugging RTL/Netlist designs.
• Strong interpersonal and problem-solving skills required.

Aufgaben

• Develop and verify IP sub-components for cellular transceiver SoCs.
• Collaborate with multidisciplinary teams for design, verification, and integration.
• Drive design topics using metrics and ensure timely project delivery.

Kenntnisse

Digital Signal Processing

Verilog/System Verilog

ASIC/FPGA Design

Debugging Skills

Scripting Languages (TCL, Python, Perl)

Interpersonal Skills

Problem-Solving Skills

English Proficiency

Ausbildung

Master's in Electrical Engineering

Ph.D. in Communication Engineering

Bachelor's in Computer Science/Software Engineering

Tools

Linux

Perforce

Jobbeschreibung

In this role, you will be a key part of the Cellular SoC IP team in Munich. As an IP Design engineer, you are responsible for developing highly customized hardware IPs for digital signal processing and integrating IPs into SoCs. You will work closely with SoC architects, System engineers, Design verification, Silicon validation teams, STA/DFT/Power specialists, and Physical designers, to develop IPs & SoCs that meet Apple devices’ power, performance, and area goals.

Description

As a Cellular design engineer, you will be responsible for developing, integrating & verifying IP sub-components for a cellular transceiver System on Chip. You would be responsible for defining and driving the implementation, timing closure, and power optimizations in close collaboration with a multi-disciplinary group from system, digital-, analog & firmware design, to design verification, and physical design teams which will support your daily work. Your work will not be limited to design. It will cover end-to-end responsibility across the project lifecycle for the IPs developed from concept to design, verification, integration, silicon validation, and finally, in-field operation.

Minimum Qualifications

• Experienced with designing low-power customized hardware for digital signal processing. Understanding of signal processing principles. Abstract modeling skills for synthesis and simulation using modern modeling language (Verilog / System Verilog).
• Proven experience in multiple sophisticated ASIC or FPGA designs, spanning from concept to productization.
• Hands-on experience with digital logic design and quality checks such as Lint and CDC/RDC.
• Proficient in using (System)Verilog, the ability to analyze RTL/Netlist designs, and outstanding debugging skills to tackle technical challenges.
• Familiar with day-to-day usage of scripting languages (e.g. TCL, Python, Perl, shell), Linux and revision control systems (e.g. Perforce), database management, and releases.
• Passion for owning/driving design topics using well-defined metrics, a strong initiative, and ownership of responsibilities, productive, and able to meet daring deadlines.
• Very good interpersonal skills, and ability to communicate abstract concepts to different stakeholders. Excellent problem-solving skills and the ability to find effective technical solutions between partners in RTL design, Firmware, System Engineering, Power, and Physical-Design teams.
• English language proficiency is a requirement for this position.

Preferred Qualifications

• Experience with on-chip communication buses & fabrics like AMBA/Wishbone and processor sub-systems would be a plus.
• Experience with SystemC/C++ hardware design modeling, high-level synthesis, and logical synthesis would be desirable.
• A master’s or Ph.D. in electrical engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent.